The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to a nonvolatile semiconductor memory device which stores multivalued data of a plurality of bits in one memory cell.
This application is based on Japanese Patent Application No. 9-096894, filed Apr. 15, 1977, Japanese Patent Application No. 9-289761, filed Oct. 22, 1997, and Japanese Patent Application No. 9-295419, filed Oct. 28, 1997, the content of which is incorporated herein by reference.
A nonvolatile semiconductor memory device which stores data of a plurality of bits, e.g., two bits in one memory cell is disclosed in, e.g., Japanese Patent Publication (KOKAI) No. 59-121696 proposed by the present inventors. In this prior art, three reference voltages are set, and each of these reference voltages is compared with the bit-line voltage of a memory cell by a sense amplifier to detect the value of the stored data.
FIG. 1 is a circuit diagram schematically showing the arrangement of this nonvolatile semiconductor memory device. FIGS. 2A and 2B are charts showing the relationship between reference voltages and bit line voltages. FIG. 3 is a block diagram schematically showing sense amplifiers. FIG. 4 is a table showing the relationship between sense amplifier outputs and stored data. FIG. 5 is a table showing the relationship between memory cell threshold voltages and stored data.
As shown in FIG. 1, a memory cell array 11 has a plurality of memory cells MC arrayed in a matrix. Each memory cell MC has a drain D, a source S, a floating gate FG, and a control gate CG. The drain D of the memory cell MC is connected to a bit line (column line) BL, the source S is connected to a source line SL, and the control gate CG is connected to a word line (row line) WL. The floating gate FG is formed in, e.g., a gate insulating film for insulting the control gate CG from the channel. Basically, the memory cell MC comprises an insulating gate type FET and changes its threshold voltage in accordance with the charged state of the floating gate FG. The memory cell MC stores data in correspondence with the threshold voltage. The memory cell array 11 shown in FIG. 1 is generally called a NOR type. In the NOR type memory cell array, the plurality of memory cells MC are integrated by connecting each memory cell MC parallel between a bit line BL and a source line SL.
Reference numeral 12 denotes a row decoder; 13, a column decoder; and 14, a column selection transistor. Reference symbol LT denotes a bit line load transistor; CT, a bit line voltage clamp transistor for setting the drain voltage of each memory cell at a predetermined value; and BC, a bias circuit for applying a bias voltage to the gate of the bit line voltage clamp transistor CT.
The memory cell MC having the drain D, the source S, the floating gate FG, and the control gate CG stores data of a plurality of bits (two bits in this example) by changing the charge amount stored in the floating gate FG. The drain D is connected to the bit line BL, the source S is connected to the source line SL, and the control gate CG is connected to the word line WL.
The word line WL selects a row of the memory cell array 11. This selection is done by the row decoder 12. The row decoder 12 decodes a row address signal (not shown) to determine the word line WL to be selected.
In, e.g., a data read mode, the bit line BL transmits, outside the memory cell MC, data in the memory cell MC electrically connected to the selected word line WL as an electrical signal. A column of the memory cell array 11 is designated by the column decoder 13. The column decoder 13 decodes a column address signal (not shown) to determine a column to be designated for a read mode. The bit line BL belonging to the designated column electrically connects the memory cell MC to a data read circuit 15 through the column selector 14. The memory cell MC connected to the data read circuit 15 changes a voltage Vout of an output node 16 of the data read circuit 15 through the bit line BL. The amount of a change in voltage of the output node 16 changes in accordance with the electrical connection state of the memory cell MC, i.e., the amount of a drain current that the memory cell MC can flow. The drain current amount changes in accordance with the threshold voltage of the memory cell MC.
Reference numeral 8 denotes a program means for performing control so as to end a data write mode when it determines, by a verify mode for checking the charge storage state of the floating gate after the write mode, that desired data has been written; otherwise, repeat the write mode and verify mode until it is determined that the desired data has been written. As the program means 8, e.g., a sequence controller is used.
Two-bit data is read out by comparing the data (bit line voltage) read out from the memory cell MC with each of reference voltages 1, 2, and 3 shown in FIG. 2A and identifying the voltage relationship relative to each reference voltage. There are four combinations of 2-bit data. These four data combinations are stored by changing the number of electrons injected into the floating gate of the memory cell to generate four different threshold voltages for the memory cell in correspondence with the injection amount.
More specifically, when the bit line voltage is lower than first reference voltage 1 which is the lowest one of the reference voltages, data "00" is stored (the lowest threshold voltage). If the bit line voltage is higher than third reference voltage 3 which is the highest one of the reference voltages, data "11" is stored (the highest threshold voltage). When the bit line voltage is between first reference voltage 1 and second reference voltage 2, data "01" is stored (the third highest threshold voltage). If the bit line voltage is between second reference voltage 2 and third reference voltage 3, data "10" is stored (the second highest threshold voltage).
The four data combinations are identified by comparing the bit line voltage with reference voltages 1, 2, and 3 by sense amplifiers 1, 2, and 3 for receiving reference voltages 1, 2, and 3, respectively, as shown in FIG. 3.
If the bit line voltage is lower than reference voltages 1, 2, and 3, outputs 1, 2, and 3 from sense amplifiers 1, 2, and 3 are at "0", as shown in FIG. 4. This is detected by a logic circuit (not shown), so D1="0" and D2="0" are output as data stored in the memory cell. Similarly, when the bit line voltage is between reference voltages 1 and 2, output 1 is at "1", and outputs 2 and 3 are at "0", so D1="0" and D2="1" are output. When the bit line voltage is between reference voltages 2 and 3, outputs 1 and 2 are at "1", and output 3 is at "0", so D1="1" and D2="0" are output. When the bit line voltage is higher than third reference voltage 3, all outputs 1, 2, and 3 are at "1", so D1="1" and D2="1" are output. FIG. 5 shows the relationship between the threshold values of the memory cell and stored data.
Data is written in the memory cell by injecting electrons into the floating gate. Before writing the data in the memory cell, data in the memory cell is erased. In a data erase mode, the control gate is set at 0 V, and a high voltage is applied to the source of the memory cell to emit electrons from the floating gate to the source of the memory cell. In a data erase mode, a high voltage is applied from a source potential circuit shown in FIG. 6. In a data read or write mode, a reference voltage, e.g., 0 V is applied from the source potential circuit to the source of the memory cell. The data erase is a kind of data write and corresponds to a state wherein the lowest threshold voltage, i.e., D1="0" and D2="0" are stored.
After this, another data is selectively written in the memory cell where the data is to be stored. To write data in the memory cell, predetermined voltages are applied to the drain and control gate of the memory cell, respectively, and the source is set at 0 V to flow a current to the memory cell, thereby injecting electrons into the floating gate. In this manner, data is written in the memory cell. As shown in FIG. 7, after the data write mode, the data is read out from the memory cell (verify read). The write and read modes are repeated until the output results from sense amplifiers 1 to 3 agree with data to be written. The data write mode is ended upon agreement. Determination whether the data agree with each other may be externally made by reading out the data outside the integration circuit or performed in the integration circuit.
In such a conventional nonvolatile semiconductor memory device, the bit line voltage can be set between, e.g., first reference voltage 1 and second reference voltage 2 in accordance with data to be stored in the memory cell. However, individual memory cells have different write characteristics. Therefore, the bit line voltage after the read mode changes depending on the write characteristics of the memory cell selected for the read mode, and the read rate largely varies depending on the selected memory cell.
More specifically, although each of bit line voltages 2, 3, and 4 is indicated by a line in FIG. 2A, in fact, each of bit line voltages 2, 3, and 4 is distributed on the upper and lower sides of the bit line voltage in accordance with the selected memory cell and has a variation r, as shown in FIG. 2B. The data read rate changes depending on the position of the selected memory cell in the distribution. For example, the read rate in the region (I) largely differs from that in the region (II).
Referring to FIG. 6, I/O 1 to I/O 8 correspond to bits of output data (8 bits), respectively. The source potential circuit is common to the plurality of output bits. Data is written by setting the source of the memory cell at 0 V and applying a high voltage to the control gate and drain of the memory cell to flow a current and inject electrons from the channel region into the floating gate. In the data write mode, data is simultaneously written in the eight memory cells corresponding to the output bits. The injection number of electrons into the floating gate is determined in correspondence with the voltage of the control gate of the memory cell. More specifically, as the control gate voltage becomes higher, the electron injection amount increases. Therefore, in the data write mode, the voltage of the control gate or drain is set in correspondence with the highest threshold voltage after the write mode. To prevent an increase in electron injection amount for a memory cell having a low threshold voltage, the electron injection time is shortened, and the write and verify modes are repeatedly performed, as shown in FIG. 7. To precisely set the threshold voltage at a predetermined value, preferably, the electron injection time is shortened to gradually inject electrons, as a matter of course. However, this requires a long data write time. In addition, to precisely set the threshold voltage of the memory cell, the control gate voltage is changed in correspondence with the threshold voltage to be set, i.e., the data write is started from a memory cell having a low threshold voltage, and then the control gate voltage is raised by a predetermined value to write data in a memory cell having a high threshold voltage. In this case as well, the write mode is performed in correspondence with each threshold voltage to be set, undesirably resulting in an increase in write time.
The sectional structure of the nonvolatile memory cell will be described below.
FIG. 8A shows a memory cell without any offset gate portion. FIG. 8B shows a memory cell having an offset gate for partially controlling the channel with the control gate.
To erase data from these memory cells, the control gate is set at 0 V, and a high voltage is applied to the drain or source for the memory cell shown in FIG. 8A, or the drain for the memory cell in FIG. 8B, thereby emitting electrons from the floating gate.
In the memory cell shown in FIG. 8A, control becomes complex because the memory cell cannot have a negative threshold voltage. However, in the memory cell with an offset gate shown in FIG. 8B, the transistor portion having a channel region to be controlled by the floating gate may have a negative threshold voltage, so control for the erase is simplified.
However, as for the memory cell size, the memory cell shown in FIG. 8A is more advantageous in reducing its size than that shown in FIG. 8B.
A general data write and erase (a kind of data write) for the above-described nonvolatile memory cell will be described next.
In the data write mode, predetermined voltages are applied to the drain and control gate of the memory cell, respectively, and the source is set at OV to flow a current to the memory cell and inject electrons into the floating gate. In the data write mode, data is read from the memory cell after the write (verify) mode, and the write and read modes are repeatedly performed until the output results from first to third sense amplifiers 1 to 3 agree with data to be written. The write mode is stopped upon agreement. Whether the data agree with each other may be determined outside the chip by reading out the data or determined in the memory chip. In both cases, detection is performed a predetermined time (strobe) after the start of the data read mode.
Before the data write mode, a data erase mode is performed. In the data erase mode, the control gate of the memory cell is set at 0 V, and a high voltage is applied to the drain or source to emit electrons from the floating gate to the source or drain. The data erase state corresponds to a lowest threshold voltage Vth1, i.e., a state wherein data "00" in FIG. 4 is stored. In the data erase mode, a verify mode is performed after the erase mode to detect whether the bit line voltage is lower than first reference voltage 1 by a sense amplifier. The erase and verify modes are repeatedly performed, and the erase mode is ended upon reaching a predetermined threshold voltage.
The data read mode of the above-described conventional nonvolatile memory cell will be described next with reference to FIGS. 9 and 10.
For the descriptive convenience, FIG. 9 shows only the memory cell MC and the load transistor LT connected to the memory cell MC in FIG. 1.
Actually, the memory cells MC are arrayed in a matrix, and the column selector transistor for selecting a column, the bias circuit BC for setting the drain voltage of the memory cell at a predetermined value, and the like are connected between the memory cell MC and the load transistor LT.
FIG. 10 is a chart schematically showing a current flowing to the memory cell MC and a current flowing to the load transistor. The voltage (output voltage) Vout at the connection point between the memory cell and the load transistor in FIG. 9 is plotted along the abscissa, and the currents flowing to the load transistor and the memory cell are plotted along the ordinate. The current flowing to the memory cell when the memory cell is selected is indicated by the solid lines, and the current flowing to the load transistor is indicated by the broken line.
Memory cell currents are shown in correspondence with threshold voltages Vth1 to Vth3 of the memory cell. When the memory cell has a threshold voltage Vth4, no current flows even when the memory cell is selected.
Intersections between the solid lines and the broken line represent the voltages Vout corresponding to the threshold voltages Vth1 to Vth3. At the threshold voltage Vth4, the voltage Vout equals a power supply voltage Vc because the memory cell is OFF.
However, as shown in FIG. 2A, four different bit line voltages are generated, and three reference voltages 1 to 3 are set among four bit line voltages 1 to 4 corresponding to the four threshold voltages Vth1 to Vth4 of the memory cell. In this case, as compared to the prior art in which two bit line voltages are generated to store 1-bit data in one memory cell, the difference between the bit line voltage and the reference voltage becomes small. This decreases the read margin, and also results in a decrease in margin for noise such as a power supply variation.
In the nonvolatile semiconductor memory device having such nonvolatile memory cells arranged in a matrix, the bit line voltage can be set between, e.g., reference voltages 1 and 2 in accordance with data to be stored in the memory cell.
However, since the write characteristics of the memory cell change depending on each memory cell, the bit line voltage between reference voltages 1 and 2 or between reference voltages 2 and 3 changes depending on the selected memory cell. Therefore, conventionally, the read rate changes depending on the selected memory cell.
More specifically, although the bit line voltage is indicated by one line in FIG. 2A, in fact, e.g., bit line voltage 2 varies with a certain distribution on the upper and lower sides of the line of bit line voltage 2 shown in FIG. 2B in accordance with the selected memory cell. Therefore, the read rate changes (varies) depending on the position of the selected memory cell in the distribution.
In addition, when the bit line voltage between reference voltages 1 and 2 or between reference voltages 2 and 3 is close to any one of the reference voltages, the read margin for the closer reference voltage becomes small.
FIG. 11 shows the distribution of the memory cell threshold voltages.
Even when the memory cell threshold voltage is to be set at one of Vth1 to Vth4, the threshold voltage varies with a certain distribution for the threshold voltage to be set because of the variation in characteristics of memory cells.
In addition, the distribution itself changes depending on each chip, as indicated by broken lines. Therefore, the read rate or read margin changes in units of chips.
As described above, in the conventional nonvolatile semiconductor memory device, the write characteristics change depending on the memory cell. Therefore, the read rate changes depending on the selected memory cell, and due to this, the read rate or read margin changes in units of chips.